### **Core Hardware** - **Main MCU**: TI Jacinto 5e (DRA623) - **Cortex-A8**: Runs **QNX Neutrino** for application-level logic - **Dual Cortex-M3s**: One runs the **Carcom RTOS** blob (CAN, LIN, watchdog, EEPROM) - **HMI Processor**: NXP i .MX6, also running **QNX**, handles graphics and user interaction - **PMIC**: S9S08DN32 - **Flash**: Macronix MX25L12835F (128Mb SPI NOR for bootloader and M3 firmware, loaded early boot) - **EEPROM**: ST M95512-R (Contains configuration and component protection keys) accessible via the M3 RTOS system only ### **Boot and System Flow** 1. **M3 Core boots first** - Loads encrypted firmware blob ("Carcom") from NOR SPI - Handles **CAN, LIN**, and watchdog **before QNX even starts** 2. **Cortex-A8 boots into QNX Neutrino** - Connects to M3 via **shared memory at 0x28010000** - IPC driver (Com2M30 / `cmsg`) handles semaphores, buffers, and mailbox IRQs 3. **NXP i.MX6 subsystem** - QNX processes relay data over **QNET** or IPC to frontend services and Java HMI